In late 2025, the semiconductor industry found itself in a peculiar state of cognitive dissonance. The headlines were dominated by the “Angstrom Era”—TSMC’s N2 (2nm) pilot runs, Intel’s 18A process claiming leadership, and the astronomical costs of High-NA EUV lithography systems priced at $380 million apiece. Yet, on the ground, procurement managers for automotive, industrial, and AI server supply chains were wrestling with a ghost from the past: shortages in mature nodes.
Specifically, Power Management ICs (PMICs), Analog chips, and Microcontrollers (MCUs) fabricated on “legacy” nodes like 28nm, 40nm, and even 90nm are facing renewed tightness. This isn’t a random fluctuation; it is a structural squeeze driven by the very AI revolution that is propelling the advanced nodes.
This deep-dive analysis explores why the “boring” mature nodes are becoming the industry’s hottest commodity, how the massive capital expenditure (CapEx) drain of advanced nodes is starving legacy capacity, and why AI servers are inadvertently creating a famine for the rest of the electronics world.
The “Spillover Effect”: How AI Servers Are Draining the Power Grid (and the Chip Supply)
The narrative of 2026 is that AI is eating the world. But physically, AI is eating electricity—and the chips required to manage it.
The Power Density Paradox
While an NVIDIA Blackwell or Rubin GPU requires cutting-edge 2nm or 3nm silicon for compute, the infrastructure supporting it relies heavily on mature nodes. A single AI server rack can now consume upwards of 120kW. Delivering this power requires a complex array of voltage regulators, PMICs, and MOSFETs.
- High-Current Demand: Modern AI accelerators demand hundreds of amperes at low voltages. The specialized BCD (Bipolar-CMOS-DMOS) processes used to make the high-efficiency PMICs for these rails are typically found on 90nm to 180nm nodes.
- The Multiplier Effect: For every advanced GPU, there are dozens of power stages, temperature sensors (Analog), and fan controllers (MCUs). The demand for these support chips has scaled linearly with the explosion in AI infrastructure, causing a massive “spillover” of demand into mature fab lines that haven’t seen significant capacity expansion in years.
Crowding Out the Little Guy
This surge in high-margin AI server demand for power chips has consequences for other sectors. Foundries, operating at high utilization rates for 8-inch wafers (projected to hit 85-90% in 2026 by TrendForce), are prioritizing these high-value AI clients. This leaves automotive and industrial buyers—who need similar 40nm-90nm capacity for their MCUs and sensors—at the back of the queue. The result is a classic “crowding out” effect, where the sheer buying power of the hyperscalers displaces traditional industries.
The Capacity War: Advanced Node CaPex vs. Mature Node Starvation
To understand the shortage, we must look at where the money is going. The semiconductor industry’s capital allocation has become heavily skewed, creating a structural underinvestment in mature capacity.
The 2nm and 18A Money Pit
The race to 2nm (and Intel’s 18A equivalent) is the most expensive industrial undertaking in human history.
- Capex Concentration: TSMC and Intel are pouring tens of billions of dollars into Giga-fabs for Angstrom-class logic. This massive outlay restricts the free cash flow available to expand legacy lines.
- High-NA EUV Costs: The introduction of High-NA EUV machines from ASML, essential for 1.4nm and below, costs ~$380 million per tool. This exorbitant cost forces foundries to focus entirely on high-margin logic to recoup investments, viewing mature nodes as “cash cows” to be milked rather than grown.
Cannibalization: Repurposing the Old for the New
Perhaps the most alarming trend for legacy buyers is the conversion of existing capacity.
- CoWoS Interposers: The “interposer”—the silicon base layer that connects HBM memory to the GPU in advanced packaging (CoWoS)—is manufactured using mature lithography (often 65nm). As demand for CoWoS skyrockets (TSMC capacity targeting 130k wafers/month by late 2026), mature node lines are being repurposed to make these interposers instead of standard MCUs or PMICs.
- Fab Conversions: Reports indicate TSMC is evaluating shifting mature-node tools from Taiwan to Singapore (Vanguard) to physically clear floor space in Taiwan for 2nm expansion. This transition creates friction and temporary supply dips, exacerbating the feeling of shortage.
Deep Dive: The Resurgence of the MCU and Analog Crunch
We are witnessing the return of “rolling constraints”—a phenomenon where shortages move in waves across different component types.
The MCU Squeeze (40nm & Above)
Microcontrollers, the brains of edge devices, are facing lead time extensions again.
- Automotive Impact: Modern vehicles are “computers on wheels,” requiring heavily on 28nm and 40nm flash-embedded processes for Zone Controllers. With 70% of automotive MCUs relying on these nodes, the lack of new capacity is a critical bottleneck.
- The “Smart” Everything: It’s not just cars. The AI PC trend requires dedicated Neural Processing Units (NPUs), but also upgraded Embedded Controllers (ECs) for thermal management and battery optimization—all vying for the same limited wafer starts.
Analog’s Silent Crisis
Analog chips (sensors, amplifiers, power converters) are often treated as commodities, but they are the interface between the digital AI world and the physical world.
- Lead Times: Sourcing for high-performance analog parts (like those from TI or ADI) is seeing lead times stretch back to 13+ weeks.
- Pricing Power: Tier-2 foundries in China and Korea, seeing utilization rise, have begun to raise prices. The era of deflationary legacy chip prices appears to be pausing.
Strategic Outlook for 2026: A Supply Chain Survival Guide
For procurement professionals and engineers, the message is clear: do not let the abundance of news about “oversupply” in consumer electronics fool you. The specific sub-segments of Power and MCU are entering a structural deficit.
1. Diversify or Die
Reliance on a single foundry source for mature nodes is risky. Qualify alternative parts from vendors who have secured guaranteed capacity or have their own fabs (IDMs like TI, though even they face pressure).
2. The “Long-Term Agreement” (LTA) is Back
Spot market availability will be volatile. Engaging in LTAs for critical PMICs and MCUs is recommended. The cost of a line-down situation far outweighs the premium of a fixed contract.
3. Design for Flexibility
Where possible, design boards to accept footprint-compatible alternatives for commodity power chips. For MCUs, this is harder due to firmware lock-in, making early forecasting essential.
FAQ: Understanding the 2026 Mature Node Shortage
Q: Why is there a shortage of old chips when 2nm is launching?
A: Investment is lopsided. Billions are going into 2nm/18A, while “old” 40nm-90nm lines are being neglected or repurposed for AI packaging (CoWoS), reducing supply for standard chips.
Q: How does AI affect power chip supply?
A: AI servers consume massive amounts of power. This creates huge demand for high-end Power Management ICs (PMICs), filling up the manufacturing lines that would otherwise make chips for cars or appliances.
Q: Will prices for MCUs go up in 2026?
A: Likely, yes. Foundries are raising prices as utilization hits 85-90%, and this cost will be passed down.
Q: What is the impact of High-NA EUV on this?
A: Directly, very little. But indirectly, the massive cost of High-NA EUV sucks up the R&D and CapEx budget of major foundries, leaving less capital for expanding mature capacity.
Conclusion
The semiconductor industry in 2026 is a tale of two cities. In the gleaming towers of the Angstrom era, engineers push the boundaries of physics with High-NA EUV and 2nm transistors. But in the sprawling suburbs of the mature nodes, a battle for survival is being fought. The “Mature Process Rebound” is a reminder that in our rush to build the artificial mind, we cannot neglect the biological need for a heartbeat—the power and control chips that bring the system to life.
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