Chiplet Summit 2026 showcased the latest modular chip designs, standards, and ecosystem growth. One standout theme was chiplet monitoring: collecting accurate lifetime health data to actively maintain reliability and optimize operation, without increasing die area.
Insights from an Industry Expert
A senior business development director with deep experience across chip design and methodology demonstrated these monitoring systems in a real commercial application.
A Deep Dive into the Live Demonstration
The demo highlighted that modern solutions go beyond basic sensors. A proprietary, machine-learning-driven software engine analyzes the design itself, including block size and the number of clock and power domains.
Intelligent Agent Configuration and Placement
The software uses design analysis to recommend a monitoring-agent configuration and the supporting hardware monitoring system. Uniquely, placement happens after place-and-route, inserting tiny agents into existing “white space” to avoid area or performance overhead. Placement is optimized to keep agents close to the circuits they monitor.
The demo ran on a high-speed optical networking chip for data centers on TSMC 5nm, showing compatibility with major design flows.
Real-Time Visibility with Continuous Performance Monitoring
With agents embedded, continuous performance monitoring periodically collects data and visualizes it, providing real-time insight into how workloads and configurations affect behavior.
Key live metrics include Margin to Timing Failure, DC Voltage, V&T Stress, Frequency, Clock Cycle-to-cycle Jitter, and Effective Cycle Time Delta, forming a health and behavior dashboard for the chip.
Active Optimization with Adaptive Voltage Scaling
The demo showcased adaptive voltage scaling (AVS): instead of running with a large lifetime safety margin, the system continuously tunes voltage down to the minimum safe level over the chip’s life.
- Immediate result: 11.64% power saving
- Projected impact: 16.28% lifespan extension
- Fully on-chip: self-contained, no cloud required
Built-In Safety and Custom Applications
When voltage was forced too low, the system detected the margin violation and corrected it within two clock cycles. Customers can also build custom on-chip apps, typically 10–50 KB.
The Future of Chiplet Reliability and Efficiency
Integrated monitoring plus on-chip analytics enables real-time visibility and active optimization for power and longevity without impacting physical design—improving reliability and efficiency for advanced chiplets.
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