Keysight EDA: Chiplet, RF & AI at DAC 2026

DAC 2026 takes place July 26–29 in Long Beach, California. Keysight Technologies is returning as a Silver Sponsor and an “I LOVE DAC” sponsor. Visit Booth #927 to see the full Keysight Design Engineering Software portfolio. The Keysight team will be onsite July 27–29 (Monday–Wednesday) for live demos and 1:1 consultations. Meetings can be booked in advance through Keysight’s official DAC event page.

Keysight Design Engineering Software targets workflow bottlenecks caused by multi-physics interactions. These interactions span RF and mixed-signal electronics, structural mechanics, thermal effects, and optics. They directly influence system behavior in manufacturing, assembly, and real-world operation. Keysight’s DAC 2026 program focuses on the challenges below.

Accelerating Agentic Design Workflows with Surrogate Modeling

• Learn about surrogate modeling, digital twins, and closed-loop validation in AI at the RF Frontier: De-Risk and Accelerate Next-Gen Custom RF/MW Design, led by Ian Rippke (Director of Global Software Solutions).
• See an Engineering Track poster on AI-enabled power amplifier behavioral modeling built on SystemVue and ADS.

Managing and Curating Data for EDA AI Workflows

Simon Rance (General Manager, Engineering Data Management) will join the panel Build vs Buy: Who Owns the Intelligence Behind Tomorrow’s Chips? The discussion will cover data infrastructure best practices for AI-powered EDA.

Die-to-Die Signal Integrity for Advanced Packaging

Explore solutions for chiplet, 3DIC, and 3D-HI interconnect challenges. A dedicated poster will present mixed-domain modeling for hatched ground planes in die-to-die interconnects. Results are validated with silicon bridge and mobile PCB test vehicles.

Pioneering Quantum Design Tools

Attend the panel From Bit to Qubit: EDA Meets Quantum, hosted by Chris Mueth (Senior Director, New Markets and Strategic Initiatives). The session will discuss how quantum EDA platforms and digital twins fit into standard chip design workflows.

Detecting Glitch Power in RTL Code

• Two posters focus on RTL-level glitch power detection and early-stage optimization:
  • Maximize RoI Through Glitch Power Optimization at Early Design Stage
  • Hunting RTL Glitches Before They Burn Power: A Practical RTL Success Story
• A third poster introduces a machine learning-driven automatic compact model extraction flow. The goal is to replace manual, expert-driven steps with a scalable and repeatable process.

What to Expect at Keysight’s Booth #927

Keysight will run live demos at Booth #927. Highlights include SOS Enterprise for governed, AI-ready engineering data storage at scale. The team will also demo RF Circuit Simulation Professional. It includes an executable RF design workflow tool for building and documenting simulation workflows, either visually or with Python.

The sessions and demos are aimed at chip, package, and RF/microwave design engineers. They also target quantum hardware teams and engineering leadership evaluating AI and governed data strategies.

DAC 2026 registration is free through the “I LOVE DAC” program. To schedule a 1:1 meeting at Booth #927 (July 27–29), visit Keysight’s official DAC event page.