RISC-V Accelerator Control & Breker VIP

Key Takeaways: RISC-V’s Unexpected Sweet Spot in Accelerator Design

RISC-V is known for a customizable ISA and low cost. That makes it attractive for storage and edge devices. It has been less obvious where it can challenge Arm at the high end.

Dave Kelf, CEO of Breker Verification Systems, highlighted a strong fit: embedded RISC-V controllers built into accelerators. This note uses AI accelerators to show why that makes sense.

A Quick Breakdown: Why AI Accelerators Need Dedicated Controllers

AI accelerators are matrix engines. They use SIMD-style parallelism in CPUs or SIMT-style parallelism in GPUs. But neither is ideal for control work, like moving inputs, loading weights, and handling outputs.

Traditionally, an Arm CPU cluster handled these tasks. It works, but it adds latency between the controller and the accelerator. Modern models are iterative, and workloads are split into many small tiles. Intermediate state lives in scratch memory. Control must stay close to compute to keep the loop tight.

Embedding RISC-V accelerator control inside the accelerator reduces that latency. It can rely on simple local links instead of a high-power, higher-latency NoC. Arm cores can still supervise at a higher level, but they are less suited for the fast inner loop.

SIMT is also harder to verify. It allows standard multithreaded programming, but it must handle divergent branches. Threads can take different paths, and results still need to stay coherent. Low-latency accelerator designs therefore need both specialized controllers and specialized verification.

Coherency is only one gap. System-level verification must also cover custom features, such as broadcast updates and integration fabrics. These are best tested with realistic workloads. In practice, teams often use synthetic stress tests that target architectural edge cases.

Breker Expands System VIP Portfolio to Address Accelerator Verification Gaps

Breker is well positioned to address these challenges. It already has a strong name in RISC-V verification. Its System Ready program is similar in spirit to Arm SystemReady. It also provides modules for cache and I/O coherency checks.

Breker is expanding its Breker Verification Systems System VIP library for AI and GPU verification. The library includes tests for SIMT thread divergence, convergence, work groups, barriers, atomics, and related accelerator behaviors.

Teams can extend the library with custom scenarios. Breker’s test synthesis engine combines user scenarios with prebuilt components to generate broader stress tests. This is especially useful for multithreaded verification, where issues often span multiple functions.

Breker is also partnering with MooresLab on spec-to-verification automation. They plan to demo the joint solution at the MooresLab booth (826) at DAC 2026, alongside MooresLab’s spec-driven verification tools.