Validated RISC-V Performance Model in 3 Months

For years, building a RISC-V performance model has been considered a slow, months-long effort that blocks design teams. Our latest collaboration shows a better method can shrink that timeline to weeks.

Breaking Down the 3-Month Development Timeline

We started the new scalar-vector performance model in April 2026.

• Week 6: Stage 1 was finished. It mapped CPU and VPU model pipeline behavior to an idealized cache, ready for microarchitecture validation.
• Week 8: The model ran real workloads end to end (Dhrystone and matrix-multiplication VPU benchmarks) and produced measured IPC, not estimates.
• Week 12: RTL performance correlation was complete. Dhrystone matched RTL, and branch-misprediction plus L1-miss behavior aligned 100% with RTL traces.

A validated scalar+vector model was ready in 3 months—a timeframe many teams associate with only starting, not finishing.

Why This Speed Is Possible: A Reusable Foundation, No Full Rebuild Required

We didn’t cut corners. We avoided starting from scratch.

Our framework already models pipelines, branch prediction, cache hierarchy, and instruction timing. It’s also reusable across microarchitectures, so new designs can be adapted rather than rebuilt.

The system is intentionally simple. Someone with basic architecture knowledge and C++ can build on it quickly. A shared instruction-decode table is used by both the model and RTL, so instruction changes update both and reduce correlation effort. Our branch-prediction approach also mirrors RTL down to the issue cycle.

With this foundation, adding components like L2 cache behavior or a full VPU model typically takes 3–5 weeks, not months. Hitting the 3-week target depends on resolving hard architectural questions early.

Smart Sequencing Keeps Timelines On Track

We tackle hard modeling challenges early to avoid late schedule slips.

If a feature is difficult and not needed for the next milestone, we defer it rather than letting it block core progress.

We apply the same sequencing to benchmarks: Dhrystone first, then matrix multiplication, then TinyML and Qwen. Each benchmark is correlated to RTL before moving on. We validate cycle-by-cycle alignment, not just IPC ratios.

What This Fast Timeline Delivers: A Demo-Ready, Usable Model Fast

The result is a usable tool, not a research artifact. It covers scalar and vector execution and is validated on real workloads, including TinyML and Qwen.

That changes customer engagement: instead of sharing only a roadmap, we can provide a working model customers can run with their own workloads.

The model is designed for teams outside our group. It includes documentation so others can run it independently.

It also beats RTL-only iteration. RTL configuration changes can require synthesis support and days of turnaround. With the performance model, teams can test cache-size or issue-width changes in minutes.

Beyond Raw Numbers: Visualize Pipeline Performance, Don’t Just Measure It

Many models only report aggregates like IPC, total cycles, or stall breakdowns. Useful, but often not diagnostic.

Our model adds built-in visualization.

The IPC Visualization tool plots per-cycle IPC across a run with color-coded instruction classes (ALU, branch, vector, vector load, vector store, CSR, divide, load, multiply, store). You can quickly see what limits throughput.

A miss-event track sits below the plot and flags D-cache misses and branch mispredictions cycle by cycle, including when both happen in the same cycle.

Users can zoom in/out. Selecting a cycle range opens a trace table showing when each instruction issues, executes, writes back, and retires, down to the PC. Vector instructions include micro-op detail for each VRF result, and the full trace can be exported to Excel.

What This Means For RISC-V IP Design Teams

For teams evaluating RISC-V IP, faster model delivery isn’t a nice-to-have; it’s core value.

Our approach uses the RISC-V open-source compiler and the Whisper instruction set, so teams can run it with the right C library and Linux version.

A model that adapts in weeks, can be handed off for self-service exploration, and keeps pace with fast design cycles turns performance modeling into a living tool that evolves with the architecture.

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• AION Silicon: Architecting Smarter SoCs with RISC-V: Balancing Performance, Flexibility, and Risk
• RISC-V and AI: The Architecture Shift Is Now