TSMC’s 0.42‑nm interface boosts 2D transistors

Researchers at Yang Ming Chiao Tung University and TSMC Corporate Research built a 0.42 nm aluminum-oxide interfacial layer for monolayer MoS₂ transistors. It protects electron transport and improves gate control. This is an important step toward post-silicon semiconductor technology.

Why Silicon Transistor Scaling Is Reaching Its Limits

Silicon transistor scaling is running into hard physical limits. Each new node is harder to shrink and more expensive to manufacture. Two-dimensional semiconductors such as monolayer molybdenum disulfide (MoS₂) are a leading alternative. Their channels can be a single atomic layer while retaining useful electronic properties. However, performance has been limited by one issue: the interface between the channel and the gate dielectric.

The Core Challenge of 2D Semiconductor Gate Design

In a field-effect transistor, the gate controls current in the channel. An insulating dielectric sits between the gate and the channel. A smaller equivalent oxide thickness (EOT) gives stronger electrostatic control. That helps reduce short-channel effects and lowers operating voltage.

Silicon benefits from mature oxidation and deposition processes. They produce uniform, high-quality interfaces. Monolayer MoS₂ is different. Its van der Waals surface has no dangling bonds, so dielectrics do not nucleate evenly.

Poor nucleation creates gaps and defects. It also introduces charge traps and local electrical variations. These problems increase leakage and hysteresis. They also scatter carriers in the MoS₂ layer.

This creates a tradeoff. A thinner dielectric improves gate control. But harsher deposition can reduce mobility and erase the advantages of 2D channels.

How The TSMC 0.42nm breakthrough Solves This Barrier

The team treated the interface as a designed device layer. They deposited an ultra-thin epitaxial aluminum layer on CVD-grown monolayer MoS₂. They then oxidized it to form ~0.42 nm of aluminum oxide. Next, they added a high-κ hafnium oxide dielectric on top.

The oxidized aluminum layer does two jobs. It provides a smooth surface so hafnium oxide can grow uniformly. It also buffers the MoS₂ from harmful interactions with the high-κ dielectric. The result is strong coupling without sacrificing electron transport.

Device Performance Test Results

With this stack, the team built short-channel, top-gate MoS₂ transistors. The EOT was about 1 nm. Devices with ~100 nm channel length reached a peak transconductance of 0.45 mS/µm. They also showed low gate leakage and little hysteresis.

Transconductance measures how strongly gate voltage modulates channel current. Higher values mean better control and stronger drive.

Critical Context: What This Advance Actually Means

The 0.42 nm number is the thickness of the aluminum oxide gate dielectric interface. It is not the gate length. This is not a 0.42 nm transistor. It is a materials and interface advance that makes dielectric scaling more feasible for atomically thin channels.

Manufacturability Potential and Remaining Challenges

This work used CVD-grown monolayer MoS₂, not exfoliated flakes. That is more compatible with large-area, potentially wafer-scale manufacturing.

Key challenges remain. The process must be uniform across wafers. Defects must be reduced. Contact resistance must drop. Reliability must improve. Integration with standard chip workflows must also be proven.

Next Steps for Commercialization

Future work will target better subthreshold swing and more stable threshold voltage. It will also focus on improved source-drain contacts. The interface must survive thermal steps and long-term electrical stress. These factors will determine commercial viability.

Broader Implications for Post-Silicon Electronics

The main lesson is that scaling will depend on interface engineering as much as on new channel materials. By combining monolayer MoS₂, a 0.42 nm interfacial oxide, and a high-κ gate dielectric, the team achieved strong electrostatic control while preserving fast electron transport. This brings 2D semiconductors closer to practical low-power logic beyond silicon.