Late this summer, Quadric will bring its programmable on-device AI solutions to three major AI conferences. Attendees will see how the Quadric Chimera GPNPU (general-purpose neural processing unit) is changing AI silicon design—from advanced processors to embedded physical AI.
Quadric’s 2026 Late Summer AI Event Tour
HotChips 2026, Stanford University | August 23–25
The tour starts at HotChips at Stanford in California. Quadric will sponsor the event and host a booth in the expo area. This stop is ideal for chip architects, SoC developers, engineering leaders, and job seekers in AI hardware. Visitors can explore the architectural choices behind Chimera GPNPU cores. They can also learn how Quadric combines neural acceleration with programmable scalar, vector, and matrix processing in one architecture. The team will also share open roles.
AI Infra Summit 2026, Santa Clara Convention Center | September 15–17
Next, Quadric will be at Booth 746 at the AI Infra Summit. The team will discuss the shift from cloud-only AI to efficient on-device inference. CTO and co-founder Nigel Drego will present “Take Control: A Processor Designed for On-Device AI” on September 16, 3:00–3:20 p.m.
AI models are evolving faster than fixed-function accelerators can keep up. Many teams end up trading off performance, power, and flexibility—or paying for costly silicon redesigns. Quadric’s fully programmable on-device AI processors and software toolchain address this. They support full inference graph execution and also run DSP and control code. Teams can add new operators and custom kernels in software. That extends silicon platforms as workloads change.
Embedded World North America 2026, Anaheim Convention Center | September 24
The final stop is Embedded World North America in Anaheim, California. At 10:25 a.m., Quadric Software Architect Mike Leonard will present “Porting Vision-Language-Action Models to Embedded NPUs: Architectural Requirements and Optimization Techniques” in the Embedded Model Deployment track.
This session is for teams building robotics, autonomous machines, automotive systems, and other physical AI products outside data centers. Vision-language-action models combine visual perception, language reasoning, and real-time control. They also push strict limits on latency, memory, bandwidth, and power. Leonard will share practical guidance for deploying these models on embedded NPUs. The talk will cover key requirements, common tradeoffs, and proven optimization techniques.
The Unifying Thread Across All Events: Total Control Over Your AI Deployment
Across all three events, Quadric emphasizes control over deployment, application pipelines, and SoC lifespan. Fixed-function NPUs often force teams to split work across accelerators, CPUs, and DSPs. Chimera GPNPU runs AI graph execution and standard C++ in one unified code stream.
The Chimera SDK supports an end-to-end workflow for ONNX models. It covers import, quantization, compilation, simulation, validation, and performance profiling—before hardware is available. This reduces integration complexity. It also lets teams adjust deployments after products ship.
Plan Your Visit to Quadric Today
Whether you focus on processor architecture, AI infrastructure, embedded deployment, or your next role, there’s a Quadric stop for you. You can book one-on-one time with Quadric’s technical experts, or visit during expo hours. Bring questions about model compatibility, performance scaling, software portability, functional safety, and power budgets. Leave with clear, actionable guidance.
Quick Event Recap: Mark your calendars for HotChips 2026 (August 23–25), AI Infra Summit 2026 (September 15–17, Booth 746), and Embedded World North America 2026 (September 24). Meet the Quadric team and see how a unified GPNPU can power high-performance, flexible, cost-effective on-device AI.
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