Huawei LogicFolding: Chip Stacking Under Export Controls

On May 25, Huawei chip executive He Tingbo introduced LogicFolding. It is a new architecture meant to boost performance without smaller transistors. Huawei launched it alongside its Tau Scaling Law. The idea is to speed up signal transmission instead of shrinking devices. It answers U.S. export controls, but big challenges remain. Heat, manufacturing yield, and design software are the main ones.

Why Huawei Can’t Follow Traditional Chip Scaling Paths

For decades, progress came from smaller transistors. Huawei can’t rely on that path now. U.S. export controls limit access to ASML EUV tools and leading-edge TSMC production. China’s top foundry, SMIC, makes 7nm-class chips with expensive deep-UV multi-patterning. That requires repeated exposures of the same layers. Each extra exposure raises cost and defect risk. SMIC’s planned 5nm-class process may cost 40–50% more than TSMC’s equivalent.

How 3D chip stacking in LogicFolding Boosts Performance

LogicFolding changes the chip’s layout. It stacks two active circuit layers face-to-face. Circuits that used to be far apart sit much closer. He’s paper describes splitting digital, analog, and memory circuits across bonded tiers. Hybrid bonding links the tiers vertically. Shorter interconnects cut delay and save energy. Huawei claims 55% higher effective density and 41% better power efficiency.

What Huawei’s Performance Claims Actually Mean

These gains mostly come from shorter wiring and better use of vertical space. They do not come from smaller transistors. So “equivalent to 1.4 nm” density by 2031 does not mean a true 1.4 nm process. TSMC’s A14 (1.4 nm) is expected in volume in 2028. That is about three years earlier than Huawei’s density target via stacking.

Core Technical Hurdles for LogicFolding Commercialization

Two problems stand out: heat and yield.

Stacked active layers trap heat. That hurts performance and long-term reliability. He has said thermal management is a central challenge.

Yield is also a concern. Defects compound across bonded tiers. If each tier yields 50%, a two-tier stack yields about 25%. If SMIC’s 5nm yields are already well below TSMC’s, stacking could widen the cost gap.

EDA Software Toolchain Bottleneck

3D chips need new EDA tools. The tools must place parts, route signals, model heat, and verify the whole stack. U.S. firms lead this market, and many tools are export-controlled. Peking University has a LogicFolding-oriented prototype, but product-grade software could take years. Huawei says the toolchain is its most important enabling investment for the next decade.

First Real-World Test of LogicFolding Coming This Fall

The first real test may come this fall. Huawei’s Kirin 9050 is expected in the Mate 90 phone. Independent benchmarks will show whether the gains hold up in volume production and sustained use. Huawei also wants to apply the approach to Ascend AI accelerators around 2030. Cooling will be even harder there.

Final Takeaway

LogicFolding shows export controls can redirect innovation. It also shows the cost of those controls. Huawei is taking a more complex, more expensive, and more yield-sensitive route because classic scaling is blocked. U.S. policymakers should keep EUV controls, review advanced-packaging dependencies, and invest in U.S. 3D-integration research. Huawei’s workaround is creative, but long-term commercial viability is still unclear.