2026 marks the inflection point for sub-2nm semiconductor manufacturing. TSMC, Samsung, and Intel are all racing to ramp gate-all-around (GAA) nanosheet transistors at the 2nm node, with ASML’s High-NA EUV scanner — the Twinscan EXE:5200 — entering production-grade qualification. But the bottleneck is no longer optics alone. The microscopic consistency of photoresist materials, specifically line edge roughness (LER), has emerged as the single most critical yield limiter at this scale.
This article examines why High-NA EUV photoresist edge roughness is the defining materials challenge for 2nm, what the industry is doing about it, and where the technology gaps remain.
What Is High-NA EUV Lithography and Why Does It Matter for 2nm?
Extreme ultraviolet (EUV) lithography uses 13.5nm wavelength light to print the finest transistor features on silicon wafers. Current production EUV systems operate at a numerical aperture (NA) of 0.33. High-NA EUV increases this to 0.55 — a 67% improvement — enabling resolution down to 8nm critical dimension (CD) and pitches as tight as 16nm in a single exposure.
ASML’s EXE:5200 is the first production-worthy High-NA scanner. Intel completed acceptance testing of the EXE:5200B in December 2025, targeting risk production of its 14A (1.4nm-class) node by 2027. IBM demonstrated full High-NA process capability at SPIE 2026, presenting a unified roadmap from image formation physics to device-level electrical results.
The key advantage of High-NA is reduced reliance on multi-patterning. At 0.33 NA, printing sub-20nm pitch features requires double or even triple patterning — each pass adding cost, cycle time, and overlay error. High-NA can achieve comparable resolution in a single exposure, theoretically simplifying the process flow.
However, this optical improvement comes with a fundamental trade-off: thinner photoresist films.
The Photoresist Thickness Dilemma at High-NA
With a higher numerical aperture, EUV photons strike the wafer at shallower angles. To avoid shadowing artifacts, resist thickness must be reduced — typically to 20–30nm or less for High-NA applications, compared to 35–50nm for standard EUV.
Thinner resist brings two competing effects:
- Reduced pattern collapse risk. The aspect ratio (height-to-width) of resist features decreases, improving mechanical stability.
- Reduced etch resistance. Less resist material means less protection during the subsequent pattern transfer etch into the underlying hard mask and device layers.
This creates an urgent need for resist materials that simultaneously deliver high resolution, low line edge roughness, and sufficient etch durability — all within a film only a few tens of nanometers thick.
What Is Line Edge Roughness (LER) and Why Is It a Yield Killer?
Line edge roughness refers to the random, nanometer-scale deviations along the edge of a printed resist feature from its intended straight-line position. At the 2nm node, where transistor gate lengths approach 5–8nm, even 1–2nm of LER represents a significant fraction of the total feature width.
How LER Impacts Device Performance
- Threshold voltage (Vt) variability. Rough gate edges cause local variations in channel length, directly modulating Vt across a chip. At 2nm GAA, acceptable Vt sigma budgets are extremely tight.
- Leakage current. Irregularities in gate edges create thin spots where gate control is weakened, increasing off-state leakage — a critical concern for mobile and AI inference chips.
- Yield loss. Stochastic edge variations can cause bridging (two adjacent lines merging) or breaks (a line failing to form), both of which are fatal pattern defects.
Industry consensus holds that LER must be controlled to sub-2nm (3σ) for reliable 2nm node manufacturing. Achieving this consistently across a 300mm wafer at production throughput remains one of the hardest unsolved problems in semiconductor patterning.
The Stochastic Challenge: Why LER Gets Worse at EUV Wavelengths
LER in EUV lithography is fundamentally driven by photon shot noise. At 13.5nm wavelength, each photon carries approximately 92 electron-volts of energy — far more than a deep-UV (193nm) photon. Fewer photons are needed per unit area to deliver a given dose, but this also means greater statistical variation in the number of photons absorbed per pixel.
This stochastic effect is described by the Resolution–LER–Sensitivity (RLS) trade-off, sometimes called the “lithographer’s triangle”:
- Higher dose reduces LER (more photons → less shot noise) but decreases throughput.
- Higher sensitivity resist improves throughput but amplifies chemical noise.
- Higher resolution demands smaller pixels, concentrating the statistical problem.
No photoresist can simultaneously optimize all three parameters. The challenge for High-NA is that while optical resolution improves, the RLS trade-off does not fundamentally change — the photon statistics remain governed by the same 13.5nm source.
Metal Oxide Resists: The Leading Candidate for High-NA EUV
Conventional chemically amplified resists (CARs) have served the industry from deep-UV through first-generation EUV. But their acid diffusion mechanism introduces blur, degrading LER at sub-20nm features.
Metal oxide resists (MORs) represent the most promising alternative for High-NA EUV:
- Higher EUV absorption. Metal compounds (tin, hafnium, zirconium) have significantly higher absorption cross-sections at 13.5nm, improving dose efficiency.
- Non-chemically-amplified mechanism. Direct photolysis avoids acid diffusion blur, offering inherently better resolution and LER performance.
- Better etch selectivity. Metal oxide frameworks provide superior etch resistance compared to organic polymers of equivalent thickness.
At SPIE 2025, multiple groups reported MOR performance approaching sub-2nm LER at 16nm pitch — a key threshold for High-NA insertion. Inpria (acquired by JSR/JM) and several Japanese resist suppliers are scaling MOR capacity to meet anticipated 2nm demand.
However, MOR integration is not straightforward:
- Metal contamination control. Tin and other metals must be kept below parts-per-billion levels in the fab to avoid device degradation.
- Outgassing management. MORs can release volatile metal-containing species during exposure, potentially contaminating the scanner optics.
- Defectivity. Particle formation in MOR films remains higher than in mature CAR processes, requiring extensive optimization.
How Are Leading Foundries Addressing the LER Challenge?
TSMC
TSMC’s N2 node entered risk production in late 2025, with volume ramp planned for 2026. TSMC has reported trial production yields of approximately 60% — strong for this stage. The company’s approach emphasizes co-optimization of resist, etch, and deposition to compensate for residual LER through downstream smoothing techniques.
Samsung
Samsung was the first to deploy GAA at its 3nm node and plans SF2 (2nm) production in 2026. Yield rates have reportedly improved to 55–60%. Samsung’s strategy includes aggressive adoption of dry resist processes and metal oxide materials, aiming to leapfrog conventional CAR limitations.
Intel
Intel’s 18A (1.8nm-class) node targets risk production in 2027 using High-NA EUV. Intel completed acceptance testing of ASML’s EXE:5200B in late 2025 and is actively qualifying resist materials in partnership with leading suppliers. Intel’s Components Research Group has published extensively on resist selection criteria for High-NA, emphasizing the need for fundamentally new resist platforms.
Rapidus
Japan’s Rapidus aims to deliver 2nm chips by 2027, leveraging IBM’s process technology and Japan’s deep photoresist supply chain (Tokyo Ohka Kogyo, JSR, Shin-Etsu). Rapidus has positioned itself as an integration hub for next-generation resist and patterning solutions.
Beyond Resist Chemistry: Post-Patterning Solutions for LER Reduction
Even with optimized resist materials, residual LER may exceed device tolerance. The industry is pursuing several post-patterning LER mitigation strategies:
Selective Atomic Layer Deposition (ALD)
Depositing a thin conformal film on resist sidewalls can smooth out high-frequency roughness. Selective ALD using materials like SiO₂ or TiO₂ has demonstrated 30–50% LER reduction in lab settings.
Directed Self-Assembly (DSA)
Block copolymer DSA can act as a defect-correcting overlay, using thermodynamic driving forces to regularize feature edges. While not yet in production, DSA has shown promise as a “healing” layer for EUV-patterned features.
AI-Driven Process Control
Machine learning models trained on in-line metrology data (CD-SEM, scatterometry) can predict and compensate for LER-induced variability in real time, adjusting etch recipes and deposition parameters on a wafer-by-wafer or even die-by-die basis.
What Does the Cost Equation Look Like?
High-NA EUV scanners carry price tags exceeding $350 million per unit. SemiAnalysis cost models indicate that despite reducing patterning steps, High-NA single patterning currently costs more per wafer than Low-NA double patterning for many critical layers.
The economic case for High-NA hinges on:
- Throughput improvement. The EXE:5200 targets 175 wafers per hour — competitive with Low-NA systems.
- Overlay accuracy. 0.7nm overlay enables tighter design rules, potentially improving die yield and density.
- Yield scaling. If LER and defectivity can be controlled, reduced patterning steps should translate to fewer cumulative defect opportunities.
The “yield wars” of 2026–2028 will determine whether High-NA delivers on its economic promise or remains a technology waiting for materials to catch up.
What Comes After High-NA? The Road to Hyper-NA and Beyond
At SPIE 2026, researchers outlined two divergent paths beyond High-NA:
- Hyper-NA EUV (NA > 0.55). Pushing numerical aperture further would improve resolution but faces severe depth-of-focus limitations and even more demanding resist requirements.
- Computational lithography + multi-patterning. Advanced mask optimization, inverse lithography technology (ILT), and AI-assisted source-mask co-optimization may extend Low-NA and High-NA systems further than previously expected.
Neither path eliminates the photoresist challenge. As long as EUV lithography relies on stochastic photon-resist interactions, LER will remain a fundamental constraint.
Key Takeaways for the Semiconductor Equipment Industry
- LER is the gatekeeper for 2nm yield. No amount of optical improvement matters if resist roughness exceeds device tolerance.
- Metal oxide resists are the front-runner for High-NA EUV, but contamination and defectivity challenges must be solved at production scale.
- Post-patterning smoothing (ALD, DSA, AI process control) will be essential complements to resist optimization.
- The cost case for High-NA is not yet proven. Materials readiness — especially photoresist performance — will determine the economic viability timeline.
- 2026 is the proving ground. TSMC, Samsung, Intel, and Rapidus are all converging on 2nm, and resist-driven yield will separate the leaders from the laggards.
Frequently Asked Questions
What is High-NA EUV lithography?
High-NA EUV lithography is the next generation of extreme ultraviolet semiconductor patterning, using a numerical aperture of 0.55 (up from 0.33) to achieve finer resolution — down to 8nm features — enabling single-exposure patterning at pitches below 20nm.
Why is line edge roughness (LER) critical at the 2nm node?
At 2nm, transistor features are only 5–8nm wide. Even 1–2nm of random edge variation causes significant threshold voltage variability, leakage current, and pattern defects — directly reducing chip yield and performance.
What are metal oxide resists (MOR)?
Metal oxide resists are a new class of EUV photoresist containing metal compounds (tin, hafnium, zirconium) that absorb EUV photons more efficiently than traditional organic resists, offering better resolution and lower LER without chemical amplification.
Which companies are leading in 2nm photoresist development?
Key players include Inpria (JSR/JM), Tokyo Ohka Kogyo (TOK), Shin-Etsu Chemical, JSR Corporation, and several emerging startups. Equipment integration is driven by ASML, TEL, and Lam Research.
When will High-NA EUV enter mass production?
High-NA EUV is expected to enter high-volume manufacturing between 2027 and 2028, with Intel’s 14A node as the first likely insertion point. Resist material qualification is the primary remaining gating factor.
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