Spec-Driven Verification: A New Era for Chip Design and Testing

The process of creating the tiny, powerful chips inside our electronics is incredibly complex. A critical phase is verification—ensuring the chip’s design works exactly as planned before it’s manufactured. Traditionally, this has been a manual, document-heavy process prone to human error. A new approach, called spec-driven verification, is emerging, promising to use artificial intelligence to automate and revolutionize this crucial step.

Understanding Verification: The Gatekeeper of Chip Design

Let’s break down the basics. When a company designs a new semiconductor chip, they start with a customer’s requirements (like “this chip needs to process video very fast”). An internal architect then creates a detailed design specification. This spec is a blueprint, often a lengthy PDF with diagrams, charts, and technical descriptions.

The verification team’s job is to prove that the final chip design perfectly matches this internal blueprint. This is different from validation, which checks if the chip meets the original customer’s intent. The verification team reads the specification documents and creates thousands of tests—the verification collateral—to stress-test the design.

The problem? This human-driven translation from document to test is not perfect. Customer needs change, architects update their understanding, and engineers can misinterpret the dense specifications at every stage. These interpretation errors can lead to costly bugs found late in the process, or worse, after manufacturing.

How AI-Powered Spec-Driven Verification Works

The core idea of spec-driven verification is to use AI agents to read, understand, and act on the design specifications automatically. The goal is to systematically eliminate those human interpretation errors.

Building a Knowledge Base from Documents

The process begins by feeding the system all relevant documents: the main PDF specs, timing diagrams, block diagrams, and protocol standards. The AI builds a robust knowledge base from this information, forming a complete digital understanding of what the chip is supposed to do.

Automated Generation of Test Plans and Benches

From this knowledge base, the system can then automatically generate the necessary verification collateral. This includes:

• A comprehensive test plan that progresses from basic functionality checks to complex stress tests.
• A full testbench architecture, which is the software environment needed to run the tests, complete with all necessary components like clock simulators and scoreboards to check results.
• Targeted tests for areas historically prone to bugs, such as recently modified parts of the design.

The Critical Element: Building Trust and Enabling Correction

For engineers to trust an AI system with such a critical task, transparency is key. A good spec-driven verification system should show you, for each test objective, exactly how it plans to execute that test based on the spec. If an engineer spots a mistake in the AI’s understanding, they must be able to correct it, and the system should learn from that feedback. This builds essential trust in agentic systems.

Furthermore, when tests are run, the system should provide clear reports. If a test fails, it should help triage the issue and pinpoint whether the root cause is in the design code, the testbench, or even in the original specification itself. When the AI claims a part of the design is fully tested (coverage), it should be able to show you the exact pages in the spec it used to verify that feature.

Addressing the Elephant in the Room: What If the Specification Is Flawed?

A systematic verification approach must account for errors at any stage. Specifications themselves can have problems. The AI system should help identify:

• Inconsistencies: Contradictions within the spec or between the spec and the actual design.
• Ambiguities: Vague descriptions that could lead to multiple valid interpretations for both design and test.
• Holes: Missing details about functionality that is implied but not explicitly stated.

Flagging these issues early allows human experts to correct the specifications upfront, preventing wasted effort down the line.

MooresLab: A Frontrunner in AI-Powered Verification

A company making significant strides in this field is MooresLab, founded by veterans from Microsoft’s design teams. They are developing the MooreIP platform, a full-stack AI suite for chip design and verification.

Their platform includes specialized AI agents: a VerifAgent for verification, along with agents for sign-off, debugging, and coverage analysis, with plans for dedicated spec and design agents. In discussions with MooresLab’s CEO, Shelly Henry, it’s clear that a major focus is on the methods to build user trust—a feature that may separate the leading tools from the rest.

They envision a future where specifications are dynamic and interactive, much like the moving photographs in the Harry Potter newspapers, making them far clearer and more intuitive to work with.

For those in the semiconductor industry, MooresLab will be showcasing their agentic tool suite at booth #826 at the upcoming DAC 2026 conference in Long Beach. Their work represents a tangible step toward a future where AI verification agents handle the heavy lifting of verification, allowing human engineers to focus on higher-level innovation and complex problem-solving.