SoC PLANNER: Automating chip design for PPA and sustainability.

Key Takeaways

• The pressure on chip design teams is immense, with billions of chips made yearly and faster-evolving demands in areas like automotive and AI.
• Manually exploring millions of possible SoC design configurations is nearly impossible and highly inefficient.
• SoC PLANNER is a new, integrated platform that automates the entire exploration process from initial goals to ready-to-use RTL code.
• It uniquely incorporates an eco-design footprint score alongside traditional PPA optimization (Power, Performance, Area).
• Real-world use cases show dramatic time savings—up to 75x faster—and more optimal design outcomes.

The SoC Design Challenge: Too Many Choices, Too Little Time

Imagine you’re an architect, but instead of designing one house, you need to plan a million different versions simultaneously, each with countless interconnected details. That’s the reality for teams designing modern System-on-Chip (SoC) semiconductors. With over a trillion chips produced annually for everything from smart cars to data centers, the requirements are changing at breakneck speed. Meanwhile, the “design space”—the number of possible configurations for a single chip—has exploded into the millions. Each configuration involves balancing conflicting goals: making it faster, more power-efficient, smaller, and getting it to market sooner. Relying on manual or semi-automated methods, even with expert engineers, is becoming unsustainable.

Introducing SoC PLANNER: The Automated Design Explorer

A collaborative three-year R&D project has culminated in a solution to this core problem: SoC PLANNER. This platform represents a fundamental shift in how chip designs are explored and defined. Funded by BPI France, it provides a breakthrough automated design exploration solution. It starts with the designer’s key performance indicators (KPIs) and explores all the way to generating the Register-Transfer Level (RTL) code needed for implementation and verification. This bridges a critical gap, shortcutting the endless back-and-forth cycles between architecture teams and implementation engineers.

The power of SoC PLANNER comes from integrating three specialized technologies into one seamless flow:

• A-DECA (Automated Design space Exploration for Computing Architectures): An engine that automatically searches and optimizes computing architectures.
• SoC Compiler: A tool that takes architectural decisions and automatically generates the corresponding RTL generation.
• PDM (Project and Design Management): A system that manages and orchestrates the complex series of electronic design automation (EDA) steps.

This integration means SoC PLANNER covers the entire “pre-synthesis” design chain. From the initial automated exploration of options to the final RTL code ready for the next stages, it’s all handled in one platform. Crucially, it also calculates an eco-design footprint score for each potential design—a unique feature that lets engineers consider sustainability from the very beginning. For large chip projects, the result is a measurable reduction in design time, resource use, and the overall timeline to first silicon.

How SoC PLANNER Works: Simplicity Meets Power

Using SoC PLANNER is designed to be intuitive. A designer inputs the parameters—like the types of processors, memory sizes, and bandwidth targets—and defines the ranges to explore. They also set the priority: is it ultra-low power, maximum performance, smallest area, or a balanced trade-off? Then, the platform’s automated design exploration engine takes over.

It autonomously estimates the area, performance (metrics like bandwidth and latency), and power consumption for millions of potential configurations across the defined space. It filters out the non-viable options and presents the best candidates. Most importantly, it doesn’t just give a report; it automatically generates the RTL generation code for those top configurations. This creates a single, seamless flow from a high-level idea to an implementable design. And for each result, that unique eco-design score is provided, offering a new dimension for making informed decisions.

SoC PLANNER in Action: Real-World Validation

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The first version of SoC PLANNER is now ready for early adopters. Its capabilities are best illustrated through two concrete use cases that move beyond traditional PPA optimization.

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Use Case 1: Designing a Low-Power AI Accelerator

This case focused on PNeuro, an energy-efficient architecture for running deep neural networks (DNNs) in embedded \”edge\” AI devices, like cameras or sensors. The design involved a host processor, shared memory, and a customizable AI accelerator block, creating a vast space of options related to cluster organization, memory setup, and clock speeds.

SoC PLANNER performed a fully autonomous, multi-objective analysis to find the “Pareto-optimal” configurations—the best possible trade-offs where improving one metric (like latency) doesn’t unfairly worsen another (like power). The tool successfully identified configurations that reduced both latency and energy use. These top-ranked designs were then automatically translated into synthesis-ready RTL code.

The Result: The automated flow provided a 30–40% reduction in exploration time compared to manual methods. It gave engineers a clear, data-driven map of the design trade-offs, enabling decisions based on KPIs rather than just intuition.

Use Case 2: Optimizing a High-Performance Computing (HPC) Chip

The second test involved a complex HPC SoC with a network connecting numerous CPU cores and peripherals. The design space contained hundreds of configurations based on core count, cache size, and memory controller settings.

Again, SoC PLANNER explored the space and pinpointed the optimal configurations balancing throughput, latency, and power. It then generated the RTL for these best-case scenarios.

The Result: The efficiency gain was staggering. An exhaustive manual evaluation would have taken roughly 150 hours. SoC PLANNER found the optimal solutions in less than 2 hours—a 75x speedup. The results were validated against industry-standard flows, confirming their accuracy and relevance.

Conclusion: A Necessary Leap Forward for Semiconductor Design

The trends are clear: chips are getting more complex, design costs are rising, and the time to market is shrinking. Incremental improvements to old workflows aren’t enough. SoC PLANNER offers a validated, concrete response. By unifying automated design exploration, pre-synthesis analysis, RTL generation, and eco-design scoring into one flow, it tackles the fundamental challenge of intelligent design selection. As proven in real use cases, it enables teams to explore vastly larger design spaces orders of magnitude faster, arrive at superior PPA optimization points, and walk away with production-ready code—fundamentally changing the economics and sustainability of SoC design.