PCIe 7.0 at 128 GT/s: Interconnects & Memory Pooling

Introduction: The Dawn of the 128 GT/s Era

High-performance computing (HPC) and AI have driven data transfer speeds to new heights. With PCI-SIG’s June 2025 release of PCIe 7.0 to members, the industry enters the 128 GT/s era—a fundamental shift requiring complete rethinking of materials, connectors, and testing.

The PCIe 7.0 release marks a critical inflection point. As data centers evolve into rack-scale computers, connectivity has become the bottleneck. Moving data at 128 GT/s per lane (512 GB/s bi-directionally for x16) enables CXL 3.x, Memory Pooling, and disaggregated Fabric systems, but requires overcoming signal integrity challenges that threaten traditional PCB designs.

This guide explores how 128 GT/s reshapes interconnect technology, drives ultra-low loss material innovations, and demands advanced testing solutions.

The Physics of 128 GT/s: Why “Fast” is “Hard”

Signal Integrity at 32 GHz

PCIe 7.0 doubles PCIe 6.0’s rate using PAM4 signaling at ~32 GHz Nyquist frequency. At these frequencies, skin effect and dielectric losses in PCBs become exponentially severe.

• Insertion Loss: FR-4 PCB traces are essentially unusable for PCIe 7.0. Signal attenuation is so extreme that signals vanish within inches on standard materials.
• Crosstalk & Reflections: At 128 GT/s, microscopic manufacturing variations cause catastrophic reflections. The PAM4 signal “eye” is tiny, leaving no error margin.

PAM4 and FEC

PCIe 7.0 uses PAM4, encoding two bits per cycle, but this reduces signal-to-noise ratio. Voltage level distinction is one-third that of NRZ signaling in PCIe 5.0.

Lightweight Forward Error Correction (FEC) compensates but adds latency. Engineers must design interconnects clean enough to keep bit error rate below 1e-4 for effective FEC without crippling cache-coherent protocols like CXL.

Material Science Innovations

Beyond FR-4: Ultra-Low Loss Materials

PCIe 7.0 ends standard PCB materials for high-speed lanes. Design teams must adopt Ultra-Low Loss (ULL) laminates.

• Dk and Df: Extremely low dielectric constant and dissipation factor are mandatory. Advanced resin systems and spread glass weaves minimize fiber weave effect, where traces see different impedances causing skew.
• Smooth Copper: Copper foil roughness contributes significantly to loss at 32 GHz. Hyper-very-low-profile (HVLP) copper provides smoother paths for high-frequency electrons.

Cabled Backplanes and Flyover Technology

The most significant PCIe 7.0 trend is moving away from PCBs for long reaches. Even the best PCB materials have excessive insertion loss for modern server channel lengths.

• Flyover Cables: Samtec’s “Flyover” and Molex’s “Genesis” systems bypass PCBs entirely. High-performance twinax cables achieve 1+ meter reaches at 128 GT/s—impossible with PCB traces without expensive retimers.
• Implications: This changes server mechanical design, requiring new cable routing and connector placements closer to ASICs.

Connector Evolution

Precision Engineering for 128 GT/s

Connectors are the most vulnerable channel points. Legacy connectors introduce excessive impedance discontinuity for PCIe 7.0.

• New Form Factors: CEM connector refinement and new, denser standards are emerging. Contact geometry optimizes to minimize stub lengths and capacitive coupling.
• Surface Mount Technology: Shift from Through-Hole to SMT accelerates. TH vias act as stubs reflecting high-frequency signals. SMT offers superior signal integrity despite mechanical challenges.

Active Electrical Cables and Smart Modules

Rack-scale architecture demands longer connections, but passive copper cables are limited (under 2 meters for PCIe 7.0).

• Smart Cable Modules: Astera Labs and Marvell pioneer Active Electrical Cables embedding retimers in connectors. These regenerate signals, enabling thinner, longer, flexible copper cables for Memory Pooling clusters.

Testing: Validating the Invisible

Testing Challenges at 128 GT/s

Testing PCIe 7.0 physical layers requires new instrumentation classes.

• Scope Bandwidth: Real-time oscilloscopes need 50-60+ GHz bandwidth to capture the third harmonic.
• Complex Equivalence: PCIe 7.0 receiver equalization (CTLE, DFE) is highly complex. Keysight, Anritsu, and Tektronix equipment must emulate receiver behaviors in software to verify signal decode capability.

Protocol Analysis

Beyond physical layer, logic validation is critical. Protocol analyzers must capture 128 GT/s traffic in real-time, decoding FLIT structures and FEC blocks to debug handshake issues.

Architectural Revolution: CXL 3.x, Memory Pooling, and Fabric

Bandwidth Enabling Disaggregation

PCIe 7.0 is the CXL 3.x backbone. While CXL 1.1/2.0 focused on memory expansion, CXL 3.x on PCIe 7.0 enables true Memory Pooling and Fabric.

• Memory Pooling: In PCIe 7.0 racks, memory isn’t trapped in specific chassis. CXL memory pools dynamically assign to any compute node. 128 GT/s minimizes remote memory latency, approaching local DDR performance.
• Stranded Memory: Pooling reduces unused RAM tied to idle CPUs, driving significant TCO savings.

Switched Fabrics and Rack-Scale Design

PCIe 7.0 enables high-radix switches interconnecting dozens of CPUs, GPUs, and memory appliances.

• Fabric Vision: Compute, memory, and storage become separate rack drawers connected by PCIe 7.0/CXL fabric, enabling independent resource scaling. AI training jobs can compose virtual servers with exact resource needs on-demand.

Conclusion: The Engineering Road Ahead

PCIe 7.0’s arrival demands departure from legacy design rules. PCBs become advanced composites; connectors become precision RF components; cables become active, intelligent systems.

For Whychip.com readers designing AI accelerators, validating signal integrity, or selecting backplane materials: 128 GT/s is fundamentally different. Success requires holistic understanding of materials, mechanics, and protocol interplay. PCIe 4.0/5.0 tools and techniques no longer suffice. Those mastering PCIe 7.0 physics will define computing infrastructure’s future.