Agentrys Builds AgentCore Chip with AI Agents

The EDA automation space is changing fast. For decades, the industry improved chip design, verification, and implementation by optimizing algorithms (for example, logic synthesis). Frontier AI now makes it possible to automate many EDA-based engineering tasks. This can raise quality and productivity and shorten time to market for semiconductor projects.

Agentrys is a next-generation EDA provider with an applied research team building the future of chip development. The company recently published a detailed white paper showing how its technology produced a production-ready chip. Below is a clearer, shorter breakdown of how Agentrys designs real chips with its multi-agent AI workforce.

The Chip Design Supply-Demand Gap Agentrys Solves

AI workloads are growing quickly, from recommenders to computer vision, speech processing, and generative models. Many new workloads need custom datapaths, numeric formats, and better energy-per-inference. That drives demand for new custom chips. But the number of experienced chip design teams has not grown at the same pace.

Agentrys aims to close this gap. The white paper says teams can spin up an autonomous chip-design workforce in minutes and deliver a sign-off-clean design in days, not the weeks or months typical of traditional teams.

The test chip is the AgentCore processor, a compact 32-bit embedded-class CPU built on an open, royalty-free ISA. It supports core integer operations (arithmetic, logic, loads/stores, branches, and jumps) plus integer multiply and a control/status register interface for performance monitoring. It leaves out heavier features like divide, floating point, and vectors to keep the design small and easier to validate.

What Is Agentrys’ Autonomous Multi-Agent Workforce?

Agentrys combines standard EDA flows with AI to create an end-to-end autonomous system. It takes a chip from initial specification to sign-off-clean layout and improves through iteration. The system is built on four pillars:

Hierarchical Multi-Agent Orchestration

A top-level orchestrator delegates work to subsystem leads. Each lead manages specialist agents for a specific part of the flow.

Governed Iteration Loops

Each optimization or debug loop runs with a fixed iteration budget. All iterations are logged. This prevents open-ended runs and pushes the system to converge.

Objective-Function Agnosticism

AgentCore optimized for XLOPS per watt. But the metric is configurable. Teams can target latency, die area, energy per inference, or a weighted mix without changing the overall closure approach.

Provenance and a Compounding Knowledge Base

Every design decision produces a verifiable artifact, stored with a checksum in a machine-readable manifest. The system also keeps a living design document and an append-only event log. A continuously updated knowledge base stores microarchitectural recipes, tool-specific workarounds, PPA-closure heuristics, and past sign-off lessons.

XLOPS is a general unit of useful work that includes floating-point FLOPS, integer TOPS, and SIMD throughput. Operations are weighted by transistor cost (for example, an FP32 fused multiply-add = 1.0, an INT32 MAC = 0.5, and a memory operation = 0.1) across nine operation classes. Full details are in the white paper.

Workflow and Performance Results for AgentCore Processor Design

For AgentCore, the system used five subsystems managed by a top-level orchestrator. Each subsystem produces a validated artifact bundle for the next stage. The main flow is linear, with feedback loops for re-implementation, re-verification, and re-closure.

Input and Setup

Ingests the chip spec and the target XLOPS-per-watt objective, then starts the full flow.

Front-End Design

Converts the spec and objectives into synthesizable RTL.

Design Verification

Checks the RTL is bit-exact against a golden ISA reference model.

Back-End Design

Runs synthesis, placement, routing, and PPA (power, performance, area) closure.

Sign-Off and Summary

Completes DRC and antenna sign-off checks, generates the provenance manifest, and compiles the final results summary.

Each subsystem runs a bounded iteration loop. A central ledger tracks how many iterations each stage uses. This governance helps long design cycles stay convergent instead of running open-ended.

The white paper reports strong results. The chart below shows how the system learns and improves performance over time.

Next Steps to Integrate AI for Semiconductor Design Into Your Workflow

If you want to bring AI into your existing chip-design flow, Agentrys positions the system as a way to extend standard EDA practice. The white paper includes real-world data. You can download it and watch an interview with the CEO to learn more.