Cross-Layer AI Co-Optimization for Chip Efficiency

Key Takeaways from the 2026 OCP APAC Summit Keynote

The OCP APAC Summit took place in Taiwan on August 11–12, 2026. Subi Kengeri (Corporate VP, Systems to Materials at Applied Materials) called AI the biggest inflection point in semiconductor history. AI demand could push the industry toward $1T in annual revenue.

But the keynote’s message was not just about growth. Traditional node scaling is no longer enough for the performance AI needs. Progress is now constrained by energy, interconnects, packaging complexity, and the speed of turning new materials into manufacturable systems.

The AI Compute Efficiency Dilemma

The efficiency gap is already visible. New AI accelerators improved cost-performance by about 3× through scaling, advanced packaging, and new architectures. Over the same period, AI server power also rose by about 3×.

Hardware is a one-time cost. Power and cooling costs continue for the system’s lifetime. That is why energy-efficient performance is now the key metric. The keynote set a bold target: a 10,000× improvement in energy-efficient AI compute by 2040.

Cross-Layer Innovations Needed for 2040

Hitting 10,000× requires parallel progress in logic, memory, and systems. Gate-all-around (GAA) transistors can cut power by ~30% and improve performance by ~15%. Backside power delivery can raise density by ~30% and improve performance by ~10%.

Memory is just as critical. High-bandwidth memory (HBM) increases bandwidth by orders of magnitude. Vertical transistors and 3D DRAM could deliver even larger gains.

Packaging ties these advances together. The talk projected future packaging could deliver up to 1,000× higher I/O density and 10× lower energy per bit.

Heterogeneous Integration Is the New Scaling Frontier

Cross-layer innovation makes heterogeneous integration the new leading edge. A typical 2000s server processor used one die (~100 mm²). Package complexity was effectively 1.

A modern high-end AI GPU can integrate 118 dies. Its package complexity factor can approach 32,000. Future system-in-package (SiP) designs could exceed 400 dies, with complexity as high as 600,000.

These systems combine logic and memory stacks, interposers, bridges, vias, embedded passives, redistribution layers, and co-packaged optics.

Interconnect Advances for Power and Bandwidth

Interconnect length drives both bandwidth and energy. Standard microbumps provide under 1,000 I/Os per mm² and use under 0.5 pJ/bit.

HBM hybrid bonding replaces longer solder connections with dense copper-to-copper interfaces. It can scale from 10,000 to 1,000,000 I/Os per mm². It can also cut energy to below 0.05 pJ/bit.

The proposed future platform combines HBM hybrid bonding, 3.5D chiplet stacking, large interposers, bridges, passives, panel processing, glass substrates, and optical links.

Why System Technology Co-Optimization (STCO) Matters

This level of complexity breaks the old sequential approach. You cannot optimize devices, then packaging, then systems in separate steps. STCO connects manufacturing process models, substrate models, package and system simulation, and die-boundary behavior into one workflow.

EDA tools are central. Thermal, mechanical, signal-integrity, and power effects must be solved together. Co-packaged optics shows why. Assembly and packaging can exceed half of production cost. Assembly + packaging + test can exceed 80%. That requires a process design kit that spans all stages.

Implications for Hyperscalers

For hyperscale cloud and AI operators, optimization must expand. Teams must evaluate package architecture, cooling, power delivery losses, repairability, and workload placement together.

The key cost metric is shifting. It is moving from cost per transistor to cost per useful function. Open interfaces matter because they let chiplets from multiple suppliers be qualified and mixed without losing system reliability.

Final Takeaways: Collaboration as a Requirement

The keynote aligned with OCP priorities and ended with an ecosystem roadmap. The industry needs modular, workload-specific chiplet architectures. It needs faster prototyping to catch new failure modes early. It needs better design-for-test methods.

Interoperable data formats and interconnect standards like UCIe are critical. Clear supply-chain ownership and known-functional-die standards are also needed.

Applied Materials highlighted its STCO platform and collaboration efforts (including OCP/OCE, UCIe work, and the EPIC innovation center). The aim is to cut innovation cycles in half by connecting universities, suppliers, equipment makers, foundries, EDA providers, and system companies.

The conclusion was direct: AI leadership will not come only from smaller transistors. It will come from co-optimizing materials, devices, packaging, cooling, power delivery, and software-visible architecture as one system.