EasyAI ECO Suite Debuts at DAC 2026

Easy-Logic is a leading provider of high-performance Engineering Change Order (ECO) tools for chip design. The company will unveil its latest product, the EasyAI ECO Suite, at the Design Automation Conference (DAC) in Los Angeles. The event runs from July 27–29, 2026.

The suite brings AI directly into the ECO workflow. It targets common pain points. These include oversized update files, slow runtimes, and timing inaccuracies. It does this with three AI-driven engines.

Transforming the Chip Design Process

The suite supports the full ECO lifecycle. It covers early synthesis (SYN ECO), test insertion (DFT ECO), and physical design (PR ECO). Each stage gets AI-based optimization.

It also addresses problems in traditional flows. Update files can become too large. Teams may repeat the same computations across iterations. Results can be hard to predict.

Dr. Xing Wei, CEO of Easy-Logic, described the impact: “Late in a chip design, saving time on each ECO directly affects time to market. The EasyAI ECO Suite is a smart, end-to-end AI integration across the change process. It delivers smaller updates, faster re-runs, and more accurate timing data. It moves AI in chip design tools from theory to practice, giving teams both speed and better control of schedules.”

The Three Intelligent Engines at the Core

The suite is powered by three specialized AI engines.

1. Auto Partition: Taming Massive Design Changes

Large ECOs can touch millions of logic gates. Conventional tools can struggle at this scale.

The Auto Partition engine uses AI to learn circuit connectivity. It follows an “analyze, split, solve” approach. It breaks large problems into smaller, manageable sub-problems.

Internal tests show it reduces the required update file by over 20% on average. In some cases, reductions reach up to 90%.

2. Learning/I-Learning: Finding the Best Possible Fix

This engine compares the old and new netlists. It looks for structural and logical similarities.

It then iteratively refines the solution. The goal is a smaller, more efficient update.

Even after manual or tool-driven edits, it can often improve results further. Customer validations show over 20% average reduction in update size. Some cases exceed 50%.

3. Smart Caching: Speeding Up Repeated Revisions

Design teams run many ECO iterations. Recomputing from scratch is costly.

The Smart Caching engine creates a “save, reuse, repeat” loop. On the first run, it learns the design structure and the changes applied. It stores that process as reusable knowledge.

On later iterations, it reuses prior results and skips repetitive work. Benchmarks show it can cut runtime by 80% or more in multi-iteration scenarios, without changing settings.

See It Live at DAC 2026

All three engines work together across the ECO workflow. Easy-Logic will demo the EasyAI ECO Suite at DAC 2026.

Attendees can see live demonstrations and discuss application-specific solutions. Visit booth #958 in Los Angeles.