New Shift-Left: FPGA Prototyping for RISC-V IP Selection

“Shift-left” used to mean starting software earlier. With RISC-V, a new shift-left is emerging: making the most important architectural choice early, which is IP selection, before the design is locked.

From Execution to Early Decisions

Teams are already good at “building the chip right” through optimization, timing closure, and verification. What often decides success now is whether the team picked the right core and IP blocks at the specification stage. A technically perfect SoC can still fail if the IP choice is wrong.

The RISC-V Problem: Too Many Options

RISC-V opens a large menu of cores and extensions. Specs and datasheets are not enough, because real workloads, custom accelerators, and timing constraints can change the result.

FPGA Prototyping as a “Test Drive”

FPGA prototyping moves from late-stage verification to early-stage decision making. It lets teams run real software at near-hardware speed and compare candidates with evidence.

• Measure real performance beyond slow simulations.
• Validate extensions and accelerators together with the core.
• Make data-driven decisions on power, performance, and features.

S2C EDA and the Prototyping Platform

S2C EDA provides high-capacity FPGA prototyping systems such as Prodigy S8-100 (based on AMD Virtex UltraScale+ VP1902) that are used by multiple RISC-V IP vendors to demonstrate and validate IP.

Bottom Line

The new shift-left is about reducing the biggest business risk in chip design: choosing the wrong IP. Using FPGA prototyping early helps teams validate choices with real workloads, and ship the right SoC, not just a well-executed one.